The subject matter disclosed herein relates to semiconductor devices and methods for fabricating the semiconductor devices. More particularly, the subject matter disclosed herein relates to semiconductor devices including a field effect transistor and methods for fabricating the semiconductor devices.
Advances in integration and miniaturization of semiconductor devices in recent years have been accompanied by rapid advances in miniaturization of transistors. To reduce the size of a transistor, the thickness of the gate insulating film has been decreased. At present, the equivalent oxide thickness (EOT) is as low as about 2.0 nm or less. If such a thin gate insulating film is a conventional SiO2 gate insulating film, the leakage current increases to a non-negligible level. Therefore, a film having a high dielectric constant (hereinafter referred to as a “high-k film”) is employed as the gate insulating film. If the high-k film is employed as the gate insulating film, the actual physical thickness can be increased to reduce a tunnel current, and the EOT can be decreased to reduce power consumption.
On the other hand, the further miniaturization of transistors has raised a problem that the capacitance of the gate electrode decreases due to depletion in the electrode. If the gate electrode is a conventional polysilicon gate electrode, the decrease in the capacitance corresponds to an increase of about 0.5 nm in the thickness of the silicon oxide film, and therefore, is not negligible compared with the thickness of the gate electrode. Therefore, the gate electrode may be comprised of a metal instead of conventional polysilicon. If the metal gate electrode is employed, the above depletion problem can be reduced.
Incidentally, if the gate electrode is formed of a polysilicon film as in the conventional art, a separate p-channel and n-channel regions (i.e., two separate regions having different work functions) can be easily formed by photolithography and ion implantation. For example, when a complementary metal oxide semiconductor field effect transistor (CMOSFET) is formed in which the gate electrode is formed of a polysilicon film, then if the gate electrode of the nMOSFET is comprised of n+ PolySi and the gate electrode of the pMOSFET is comprised of p+ PolySi, a low threshold is obtained. This technique (dual work function) is widely used.
However, typically, different work functions are imparted to the metal gate electrodes using a technique corresponding to that which is used when the polysilicon gate electrodes are formed, i.e., implantation of impurities of different types into the respective regions after deposition of a single film. Therefore, it is difficult to easily change the work function. In this circumstance, for example, a technique has been studied in which the metal gate electrodes in the n-channel and p-channel regions are comprised of a single or different metal materials, and fluorine or carbon is implanted into the metal material or materials of the metal gate electrodes (see, for example, Japanese Patent Publication No. 2006-157015).
There are roughly two processes for forming the metal gate electrode. Specifically, in one of the two processes, a metal electrode layer is previously formed in steps in which a gate resist pattern is formed by photolithography and a gate electrode is processed (gate-first process). In the other process, a metal electrode layer is newly formed in a step after a gate resist pattern is formed by photolithography and a gate electrode is processed (gate-last process). The gate-first process can be performed using a process flow which is almost the same as the technique of forming the polysilicon gate electrode, which has been employed before the technique of forming the metal gate electrode. Therefore, high-temperature annealing etc. required for formation of interfaces between the semiconductor substrate, gate insulating film, metal layer, and silicon layer which are located at the gate electrode, can be applied.
On the other hand, the gate-last process requires a lot of additional steps, such as the step of removing a silicon layer and a metal layer, etc., in a gate electrode which has been once formed, the step of burying a metal layer, and the step of removing and polishing the metal layer, etc., and therefore, the process cost is high. It is also necessary to form an interface located at the gate electrode after extension implantation and source/drain implantation required for formation of the transistor are performed. Therefore, a high-temperature thermal treatment etc. would cause a degradation in the performance of the transistor, and therefore, a sufficient thermal treatment cannot be performed. Therefore, it is difficult to carry out the process, and it is necessary to address variations in the transistor.
Therefore, the gate-first process, which is a promising low-cost process for future CMOS device formation, has been extensively studied. In the gate-first process, a CMOS device is typically formed as follows.
FIGS. 23A-23D, 24A-24D, and 25A and 25B are cross-sectional views showing successive steps in a method for fabricating a conventional semiconductor device. Note that, in each figure, a region on the left-hand side of the drawing sheet is a region 100N in which an n-channel MIS transistor is formed, and a region on the right-hand side of the drawing sheet is a region 100P in which a p-channel MIS transistor is formed.
Initially, as shown in FIG. 23A, an isolation structure 102 is formed in a semiconductor substrate 101, and thereafter, a p-well and an n-well are formed in the regions 100N and 100P, respectively, of the semiconductor substrate 101. Next, a high-k film (e.g., a HfO2 film etc.) is formed as a gate insulating film 105 on an entire surface of the semiconductor substrate 101. Next, a metal film (e.g., TiN etc.) for a metal gate electrode is deposited as a gate electrode material 107 on the gate insulating film 105.
Next, as shown in FIG. 23B, a resist pattern 108 having an opening only in the region 100P is formed, and thereafter, carbon ions are implanted into the gate electrode material 107 using the resist pattern 108 as a mask, to form a pMIS metal material 109. Next, the resist pattern 108 is removed.
Next, as shown in FIG. 23C, a resist pattern 110 having an opening only in the region 100N is formed, and thereafter, fluorine ions are implanted into the gate electrode material 107 using the resist pattern 110 as a mask, to form an nMIS metal material 111. Next, the resist pattern 110 is removed.
Next, as shown in FIG. 23D, a polysilicon film is deposited as a gate electrode material 112 on an entire surface of the semiconductor substrate 101.
Next, as shown in FIG. 24A, a gate resist pattern 113 is formed.
Next, as shown in FIG. 24B, the gate electrode material 112 is processed into a gate electrode shape using the gate resist pattern 113 as a mask.
Next, as shown in FIG. 24C, the gate resist pattern 113 is removed. Next, the pMIS metal material 109 and the nMIS metal material 111 are removed by anisotropic etching until the gate insulating film 105 is exposed. Next, after the removal of the pMIS metal material 109 and the nMIS metal material 111, the exposed gate insulating film 105, and an interface layer 106 located therebelow, are removed by wet etching etc.
Next, as shown in FIG. 24D, an insulating film (e.g., a TEOS film or a SiN film, etc.) is deposited on an entire surface of the semiconductor substrate 101, and thereafter, an etch-back process is performed by anisotropic dry etching, to form offset sidewalls 114. Next, an extension implantation layer 115 is formed by ion implantation in surfaces of the semiconductor substrate 101 in the regions 100N and 100P separately.
Next, as shown in FIG. 25A, an oxide film (e.g., a TEOS film or an NSG film, etc.) is deposited as a lower sidewall film 116 on an entire surface of the semiconductor substrate 101, and thereafter, a SiN film is deposited as an upper sidewall film 117. Next, an etch-back process is performed by anisotropic dry etching on the multilayer film of the lower and upper sidewall films 116 and 117 to form sidewalls 118 including the offset sidewall 114, the lower sidewall film 116, and the upper sidewall film 117.
Moreover, a source/drain implantation layer 119 is formed by implanting arsenic (As) and phosphorus (P) ions into the region 100N and boron (B) ions into the region 100P. Next, the impurities introduced by the ion implantation are activated by an activation thermal treatment.
Next, as shown in FIG. 25B, Ni, which is a high melting point metal, etc. is deposited by sputtering etc. on an entire surface of the semiconductor substrate 101, and a thermal treatment for silicidation is then performed. Thereafter, an unreacted region after the silicidation is removed by wet etching. As a result, a silicide layer 121 is formed in each of a surface of the source/drain implantation layer 119 in the surface of the semiconductor substrate 101 and a surface of the gate electrode material 112.